1. Field of the Invention
The present invention relates to a measuring apparatus that measuring a signal-under-test, a testing apparatus for testing a device under test and an electronic device. More specifically, the invention relates to a measuring apparatus, a testing apparatus and an electronic device for measuring jitter in a signal-under-test outputted out of the device under test.
2. Related Art
There has been known a test for measuring jitter in a signal-under-test outputted out of an electronic device such as a semiconductor circuit as an item for testing the electronic device. For example, jitter of such signal-under-test is measured by a time interval analyzer, an oscilloscope or the like by inputting the signal-under-test thereto. The time interval analyzer or the like allows such jitter to be calculated by measuring phase errors of edges in the signal-under-test for example.
Still more, there has been known a functional test for judging whether a pattern of a signal-under-test outputted out of an electronic device is corresponding to a pattern of an expected values as an item for testing the electronic device. In this test, a testing apparatus detects a data pattern of the signal-under-test by comparing a voltage values of the signal-under-test outputted out of the electronic device with threshold voltage when a predetermined test pattern is inputted to the electronic device. Then, it judges whether or not the data pattern coincides with the pattern of the expected values.
It has been thus necessary to prepare the apparatus for measuring jitter and the apparatus for testing functionality of the device in order to carry out the jitter test in addition to functional tests as described above. Therefore, it has been costly to carry out the jitter test.
Still more, the apparatus of functional test compares the voltage value of the signal-under-test with the threshold voltage at preset timing. Therefore, it can detect the edge position or timing, over which the data pattern of the signal-under-test transits bit by bit, by shifting the comparison timing. It is then conceivable to be able to measure jitter by utilizing this function, i.e. by using the apparatus for performing functional testing.
However, the conventional apparatus for functional testing sets and uses sampling timing s based on test rate synchronized with the operating period of the signal-under-test. Therefore, for each test rate it is necessary to set phase of the sampling timing in order to gradually shift the relative phase of the sampling timing with respect to the signal-under-test within each test rate. It has been thus necessary to carry out the cumbersome timing setting in order to carry out the jitter test, and it has taken a significantly long time for testing. Still more, its measuring accuracy is insufficient and is not suitable for tests because its timing is shifted in the relative phase fashion. An aspect of the present invention solves a problem for selecting sampling timings at which an output signal from the device under test is sampled by using the apparatus for functional testing in order to realize both efficient and accurate measurements of jitter in the signal-under-test.
Additionally, it has not been known that how to process the measurement data in order to efficiently and accurately obtain the jitter characteristic or another measure in the signal-under-test from the measurement data, which retain the same jitter information as that of the signal-under-test as the result of solving the above described problem. Thus, an aspect of the present invention provides solution to a problem that how to efficiently and accurately obtain the jitter characteristic of the signal-under-test from the measurement data of the signal-under-test.
When jitter is measured by using an oscilloscope or the like, the signal-under-test to be inputted therein contains amplitude noise component in addition to the timing noise component. Therefore, it has been difficult to accurately measure only the timing noise of the signal-under-test. An aspect of the present invention demonstrates that the timing noise of the signal-under-test can be accurately measured by eliminating an effect of the amplitude noise component in the signal-under-test by using a voltage comparator provided in the apparatus for functional testing. Additionally, an aspect of the present invention demonstrates that a state of the signal-under-test (i.e. a state indicating whether the logical value of the signal-under-test is an expected logical value or not) can be sampled by using the voltage comparator.
Moreover, an aspect of the present invention demonstrates that many kinds of various measurements can be performed by using the apparatus for functional testing, which has a number of measurement pins. For example, it demonstrates that a deterministic skew and random skew in a plurality of signal-under-tests can be efficiently and accurately measured.
Here, the related art have been disclosed, for example, as in 1) U.S. Patent Application Publication No. 2005/069031 and 2) U.S. Patent Application Publication No. 2005/0243950.
The document 1) discloses a technique for calculating the probability density function of jitter in the signal-under-test by means of undersampling.
However, the invention disclosed in the document 1) aims to detect only jitter for only one edge type, for example, described in paragraph 0131 as “jitter for only one EDGE type is measured and the other edge is ignored.” Accordingly, it has a disadvantage that jitter for the other edge type can not be measured. Additionally, since a method of measuring cumulative distribution function is employed, it is necessary to perform a pattern-matching and also necessary to implement a state machine. For example, in order to detect 01 bit pattern (leading edge), it is necessary to implement the state machine being capable of comparing two bit patterns. Moreover, the invention disclosed in the document 1) can not measure jitter in the time domain and frequency domain.
For example, in order to measure jitter for the leading edge, it is necessary to check bits adjacent to each other to detect “01” pattern as described in paragraph 0131 of the document 1). Firstly, a beat frequency signal Q is fed into a shift register having 2J-bit width in a general purpose circuit shown in FIG. 9 of the document 1) in accordance with sampling frequency fs. At this time, when the bit pattern is “01”, “1” is fed into the shift register as described in paragraph 0076 of the document 1).
Next, a state machine 110 shown in FIG. 9 and FIG. 8B of the document 1) continuously counts the bit number of “1” (corresponding to “01”) which are continuously inputted (=state 2). When a predetermined number of “1” bits are continuously inputted, the carry Cout of a counter 132 is outputted to a counter 134 and a middle of rising edge state 3 is recognized. Further, when the counter 134 outputs the carry Cout to a counter 136, the discrete value of the counter 136 at a bin position in a cumulative distribution function CDF is increased. When the value of the counter 132 is equal to the value of the counter 136, the discrete value of a counter 138 at the bin position in the cumulative distribution function CDF is added by 1. Thus, the cumulative distribution function CDF is measured as described in paragraph 0102 of the document 1).
As described above, the invention disclosed in the document 1) is not suitable for a testing apparatus for testing an electronic device. That is, a method being capable of measuring jitter without limiting the edge type is desired for a testing apparatus (For example, jitter appears as a plurality of impulses being adjacent to each other in FIG. 34C of the present specification.
Moreover, it is desired that jitter can be measured in both the time domain and frequency domain in addition to the probability density function (PDF). Finally, in order to enable to perform a jitter test without changing the configuration of the current testing apparatus, it is necessary to measure by comparing a 1 bit of sample value with a 1 bit of expected value without using a pattern-matching which requires such as the state machine as mentioned above.
Moreover, it is described that jitter can be analyzed by using a memory and a computer for the testing apparatus in paragraph 0129. However, how to analyze jitter is not disclosed therein.
In the document 2), an analyzing method of the spectrum of an error signal by using a critical sampling in a bit error rate measurement system is disclosed. As shown in FIG. 2 of the document 2), for each bit time interval a single sample point is sampled. That is, 2 points per period is sampled, so that the sampling is referred to as the critical sampling.
According to the document 2), it insists on disclose and providing of the method for measuring the jitter spectrum. However, it has an essential defect that in order to calibrate the measurement value with the jitter value, it requires the phase modulation of clock signal using the calibration signal. This is because of critical sampling: It is impossible to measure the signal level accurately using critical sampling, especially the signal level of the clock, which is a critically important measure for estimating a jitter value being defined as the signal-to-noise (or jitter in this case) ratio.
By the way, an error signal is the result of comparing the expected data with the input logical data. Therefore, in order to efficiently observe the error signal by the technique disclosed in the document 2), the time offset of a sampling timing has to be adjusted such that the bit value transition can be critically sampled at the adjusted timing point.
Accordingly, it is an advantage of the invention to provide a measuring apparatus, a testing apparatus, and an electronic device which are capable of solving the above-mentioned problem. This advantage may be achieved through the combination of features described in independent claims of the invention Dependent claims thereof specify preferable embodiments of the invention.